Standardized FET integrated circuit layouts have heretofore been based upon the master-slice method. In the master-slice method, a standardized array of diffusion shapes is deposited on the wafer with the intention of imparting all circuit personality by means of variations in the location and interconnection of the overlying metallized gates and thin oxide. Master-slice has the same basic diffusion pattern. A December, 1967 article by A. Weinberger in the IEEE Journal of Solid State Circuits, Vol. SC2, No. 4, Pages 182-190, illustrates the master-slice method. An FET integrated circuit arrangement is disclosed consisting of a spaced parallel diffusion pattern to be embodied in a semi-conducting wafer, with interconnection metallization to be embodied on a higher level. The layout method comprises the steps of repeating the diffusion rows across the chip to form the fixed, master slice diffusion pattern. Wafers with this fixed diffusion pattern are stock piled for future circuit personalization by means of locating metallized gates thereover. The layout permits but a single degree of freedom in circuit personalization through the placement of metallized gates over the fixed diffusions forming the FET devices. Variations in the personalized interconnection of the diffusion rows can only be accomplished by varying the position of the metallized gates along the respective diffusion row axes and the interconnection of those metallized gates by means of via-holes with the fixed diffusions. This prior art standardized one dimensional layout. The method works well for moderate density integrated circuit devices with a low order of logical complexity, however, its inherent lack of flexibility in the location and interconnection of device nets precludes its applicability to high density integrated circuit applications embodying complex logical functions.
Greater circuit layout flexibility and packing density is required to obtain higher logic power per unit area for large scale integrated circuits.